TSMC Pauses on ASML's High-NA EUV Machines for A13 Node — A $410M Price Tag, Alternative Scaling, and a Defer-Not-Abandon Signal to the Semiconductor Industry
AI / AI Tech Trends | 4 min read
TSMC — the world's leading chipmaker and ASML's largest customer — has officially announced it has no current plans to purchase ASML's High-NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography machines for its upcoming A13 process node, with any adoption now expected no earlier than 2029. The announcement was made at TSMC's 2026 North America Technology Symposium by Deputy Co-Chief Operating Officer Kevin Zhang, who stated that the A13 node does not necessitate the upgrade — a posture widely characterised by analysts as "defer, not abandon." Each High-NA EUV machine from ASML carries a price tag of more than €350 million (~$410 million) per unit. The announcement sent ASML shares lower by 3.3% in a single day, raising fresh questions about the timing, economics, and competitive dynamics surrounding the world's most advanced manufacturing tools — and whether the cost of cutting-edge lithography is creating a new dynamic in how the semiconductor industry scales.
The A13 Node — A Direct Shrink of A14, Full Backward Compatibility, 2029 Production
At the same symposium, TSMC unveiled its full process roadmap through 2029. Following the mass production of its N2 process (expected in first products in 2026), TSMC will advance through N2P/N3A (2026), N2X/A16 (2027), A14/N2U (2028), and A13/A12 (2029). The A13 node — equivalent to 1.3 nanometres — is a direct shrink of A14, with full backward compatibility. The A12 (1.2nm) will be launched around the same time as a further enhancement. Kevin Zhang said he was "amazed" that TSMC's R&D team managed to keep scaling with existing EUV tools — achieving the density, performance, and power efficiency gains required for A13 without needing to step up to High-NA. For the A14 node, TSMC uses advanced nanosheet transistor architectures that deliver up to 15% higher performance or 30% lower energy consumption — without High-NA. TSMC will keep a small number of High-NA units for research purposes in the meantime, maintaining access to the technology while deferring volume investment.
The Impact on ASML — €60 Billion Revenue at Risk, Intel's Different Bet
ASML had previously declared High-NA EUV production-ready for volume orders in February 2026, and had projected the technology generating up to €60 billion in revenue by 2030. TSMC's decision to defer adoption until 2029 forces ASML to recalibrate its near-term expectations for the technology's adoption curve — and introduces uncertainty for investors who had expected faster uptake. Notably, Intel is taking a different approach: its 14A node and subsequent generations are set to adopt High-NA EUV starting in 2027–2028, making Intel the earliest volume adopter. Samsung is also deploying High-NA systems. The broad commercial breakthrough for High-NA EUV is still expected from 2027 onward — TSMC's timeline slip does not eliminate the technology's long-term trajectory, but it does confirm that in advanced chipmaking, the largest customers move at their own economic pace, not the equipment vendor's preferred schedule. TSMC customers including Nvidia, Apple, and Google have been given a clear signal: TSMC is confident about advancing its roadmap without jumping into ASML's most expensive new equipment — at least for now.
Key Takeaways
- • TSMC (world's leading chipmaker; ASML's largest customer; Deputy Co-COO: Kevin Zhang) has announced no current plans to purchase ASML's High-NA EUV lithography machines for its A13 node — with adoption deferred to 2029 at the earliest. Announced at TSMC's 2026 North America Technology Symposium (22 April 2026). ASML shares dropped 3.3% on the announcement. High-NA EUV machine cost: €350M+ (~$410M) per unit. Analyst framing: "defer-not-abandon."
- • TSMC process roadmap through 2029: N2 (2026, first products); N2P/N3A (2026); N2X/A16 (2027); A14/N2U (2028); A13/A12 (2029). A13: equivalent to 1.3nm; direct shrink of A14; full backward compatibility with A14. A12: 1.2nm; further A14 enhancement; launching alongside A13. Neither A13 nor A12 requires High-NA EUV. A14 nanosheet architecture: up to 15% higher performance or 30% lower energy consumption without High-NA. Kevin Zhang said he was "amazed" TSMC's R&D kept scaling on existing EUV. TSMC retains a small number of High-NA units for research.
- • Why TSMC is deferring: two drivers — (1) Cost: €350M+ per machine is prohibitively expensive for volume adoption when existing EUV delivers the required scaling; TSMC wants to extract maximum value from its existing machine park before investing billions again. (2) Technology: TSMC's R&D team has developed alternative scaling methods — nanosheet architectures and process optimisations — that achieve A13/A14 density and performance targets without High-NA EUV. The combination of cost discipline and engineering innovation makes High-NA unnecessary for TSMC's immediate roadmap.
- • ASML impact and competitive dynamics: ASML had declared High-NA production-ready for volume orders (February 2026) and projected up to €60 billion in revenue from these systems by 2030. TSMC's deferral forces a near-term revenue recalibration. Intel: adopting High-NA for its 14A node and subsequent generations starting 2027–2028 — the earliest volume adopter. Samsung: also deploying High-NA systems. Broad commercial breakthrough for High-NA EUV still expected from 2027 onward — TSMC's deferral is a timing shift, not a technology rejection. TSMC customers Nvidia, Apple, and Google receive confirmation that their chip roadmaps advance on TSMC's schedule, not ASML's.
- • Strategic significance for AI infrastructure: TSMC's A13 and A12 nodes at 1.3nm and 1.2nm represent the process technology underpinning the next generation of AI chips — from Nvidia GPUs to Apple silicon to custom AI accelerators from Google and other hyperscalers. The "defer-not-abandon" posture signals that TSMC believes it can deliver the transistor density, performance, and power efficiency that AI chip customers demand through 2029 using existing and optimised EUV technology — without the disruptive cost of a €350M+ per-unit technology transition. For the broader AI infrastructure buildout, this means the supply chain of leading-edge AI chips is not at risk from a lithography technology gap — TSMC's roadmap confidence directly flows through to Nvidia, Apple, and Google's AI chip production timelines.